1. Field of the Invention
The present invention relates to an integrated electronic module which is equipped with at least one hardware error infeed for checking purposes as well as a number of terminals. The present invention also relates to a method for simulating hardware errors on an integrated electronic module which is equipped with at least one hardware error infeed for testing purposes.
2. Description of the Prior Art
For purposes of testing electronic devices, particularly by customers when purchasing from a manufacturer, hardware errors are simulated and the corresponding correct response of the device, among other things, is thereby checked. Interruptions of lines or plug contacts, shorts, inversions, etc., are, therefore, simulated. The test is usually directed to whether and to what extent such an error can be reliably detected, localized, traced to its possible cause and, finally, reported in the device. The simulation of hardware errors in integrated electronic modules (ICs), particularly application-oriented integrated modules (ASICs), turns out to be difficult, if not impossible, to the extent that the internal components and lines of an IC are shut off from direct access.
Until now, error infeeds have been realized through intermediate adapters, switches, jumpers, special assemblies, extra busses and various other methods. A functional hardware error--e.g., inversion of the data or addresses, generation of an interrupt and other similar errors--has been fed in through adjustment of the switch, insertion of the special assembly, and so on. The methods utilized until now presuppose a one-time, expensive development, documentation, production and test of the required equipment, which is utilized only for purchase in the presence of the customer. Furthermore, these methods are not uniform and not standardized. In commissioning, this demands repeated and precise studying by the personnel of the methods applied in each individual system. Also, either one has to be satisfied with generating a relatively low number of errors "by hand" or one has to create a separate means for controlling the error generation which, above all else, results in additional hardware outlay.
It is thus an object of the present invention to develop a hardware error infeed that can be executed both simply and uniformly for different types of ICs and that can keep the required outlay for additional hardware components relatively low.